publications

2023

1. Systolic Array for Parallel Solution of the Robust Kalman Filter Used for Attitude and Position Estimations in UAVs

   Leandro José Evilásio Campos , Marco Henrique Terra , Ricardo Menotti, and 1 more author

   In 2023 International Conference on Unmanned Aircraft Systems (ICUAS) , 2023

2019

1. Design of power-efficient FPGA convolutional cores with approximate log multiplier

   Leonardo Tavares Oliveira , Min Soo Kim , Alberto A. Del Barrio , and 2 more authors

   In ESANN 2019 - Proceedings, 27th European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning , 2019

2018

1. Experimenting with a Multi-Approach Testing Strategy for Adaptive Systems

   Bento R. Siqueira , Misael Costa Júnior , Fabiano C. Ferrari , and 3 more authors

   In Proceedings of the XVII Brazilian Symposium on Software Quality , 2018

   Abs

   Context: Testing adaptive systems (ASs) is particularly challenging due to certain characteristics such as the high number of possible configurations, runtime adaptations and the interactions between the system and its surrounding environment. Therefore, the combination of different testing approaches in order to compose a strategy is expected to improve the quality of the designed test suites. Objective: To devise and experiment with a testing strategy for ASs that relies on particular characteristics of these systems. Method: We ranked testing approaches for ASs and devised a strategy that is composed of the three top-ranked ones. The rankings address the challenges that can be mitigated by the approaches, activities from a typical testing process, and characteristics observed in some AS implementations. The strategy was applied to two adaptive systems for mobile devices. Results: The approach was applied to both systems. We observed partial gains in terms of fault detection and structural coverage when results are analysed separately for each system, even though no improvements were obtained with the application of the third approach. Conclusion: The strategy, despite being incipient, is promising and motivates a deeper analysis of results and new experiment rounds. Furthermore, it can evolve as long as the rankings are updated with new approaches.

2016

1. Characterisation of Challenges for Testing of Adaptive Systems

   Bento Rafael Siqueira , Fabiano Cutigi Ferrari , Marcel Akira Serikawa , and 2 more authors

   In Proceedings of the 1st Brazilian Symposium on Systematic and Automated Software Testing , 2016

   Abs

   Context: Exercising the implementation of an adaptive system (AS) effectively, in order to detect faults, is not a trivial task. This is due to characteristics of this type of systems, such as the high number of configurations and runtime adaptations. In this context, the characterisation of challenges for testing ASs may support the definition of suitable testing strategies. However, such characterisation is currently spread over several studies in the literature. Objective: analysing testing-related challenges for ASs which are described in the literature, and establishing a generic classification. Method: we extended a Systematic Literature Review (SLR) of studies that address challenges for AS testing. By analysing the combined results (original and extended), we mapped descriptions found in individual studies, based on their similarities, in order to create a list of generic challenges. Results: a list of 12 generic challenges based on 34 specific ones described by several authors. Additionally, we analysed the relationship between the challenges and inherent properties of ASs. Conclusion: different terminology, varied levels of details and particular contexts (e.g. specific AS implementations) are recurring problems related to the characterisation of challenges for testing ASs. Generalisations such as the one proposed in this work may help researchers and practitioners do devise customised testing strategies that focus in recurring, inherent properties of ASs.

2. Towards the Characterization of Monitor Smells in Adaptive Systems

   Marcel A. Serikawa , André de S. Landi , Bento R. Siqueira , and 4 more authors

   In 2016 X Brazilian Symposium on Software Components, Architectures and Reuse (SBCARS) , 2016
3. A Special-Purpose Language for Implementing Pipelined FPGA-Based Accelerators

   Cristiano B. Oliveira , Ricardo Menotti, João M. P. Cardoso , and 1 more author

   2016

   Abs

   A common use for Field-Programmable Gate Arrays (FPGAs) is the implementation of hardware accelerators. A way of doing so is to specify the internal logic of such accelerators by using Hardware Description Languages (HDLs). However, HDLs rely on the expertise of developers and their knowledge about hardware development with FPGAs. Regarding this, efforts have been focused on developing High-Level Synthesis (HLS) tools in an attempt to increase the overall abstraction level required for using FPGAs. However, the solutions presented by such tools are commonly considered inefficient in comparison to the ones achieved by a specialized hardware designer. An alternative solution to program FPGAs is the use of Domain-Specific Languages (DSLs), as they can provide higher abstraction levels than HDLs still allowing the developers to deal with specific issues leading to more efficient designs and not always covered by HLS tools. In this chapter we present our recent work on a DSL named LALP (Language for Aggressive Loop Pipelining), which has been designed focusing on the development of FPGA-based, aggressively pipelined, hardware accelerators. We present the recent LALP extensions and the challenges we are facing regarding to the compilation of LALP to FPGAs.

2015

1. LALPC: Exploiting Parallelism from FPGAs Using C Language

   Lucas F Porto , Marcio M Fernandes , Vanderlei Bonato , and 1 more author

   Journal of Physics: Conference Series, Oct 2015

   Abs

   This paper presents LALPC, a prototype high-level synthesis tool, specialized in hardware generation for loop-intensive code segments. As demonstrated in a previous work, the underlying hardware components target by LALPC are highly specialized for loop pipeline execution, resulting in efficient implementations, both in terms of performance and resources usage (silicon area). LALPC extends the functionality of a previous tool by using a subset of the C language as input code to describe computations, improving the usability and potential acceptance of the technique among developers. LALPC also enhances parallelism exploitation by applying loop unrolling, and providing support for automatic generation and scheduling of parallel memory accesses. The combination of using the C language to automate the process of hardware design, with an efficient underlying scheme to support loop pipelining, constitutes the main goal and contribution of the work described in this paper. Experimental results have shown the effectiveness of those techniques to enhance performance, and also exemplifies how some of the LALPC compiler features may support performance-resources trade-off analysis tasks.

2. Netfpga: Processamento de pacotes em hardware

   Pablo Goulart , Ítalo Cunha , MA Vieira , and 2 more authors

   Minicursos do Simpósio Brasileiro de Redes de Computadores-SBRC, Oct 2015

2014

1. Geração automática de hardware a partir de programas descritos em linguagem C com pragmas

   Lucas Porto , and Ricardo Menotti

   In Anais do XV Simpósio em Sistemas Computacionais de Alto Desempenho , Oct 2014

2012

1. LALP: A Language to Program Custom FPGA-based Acceleration Engines

   Ricardo Menotti, João Manuel Paiva Cardoso , Marcio Merino Fernandes , and 1 more author

   International Journal of Parallel Programming, Oct 2012

2011

1. LALP: a language for loop parallelism exploitation in reconfigurable computing

   Ricardo Menotti

   Oct 2011

2010

1. LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável

   Ricardo Menotti

   Universidade de São Paulo , Oct 2010
2. On Using LALP to Map an Audio Encoder/Decoder on FPGAs

   Ricardo Menotti, João M. P. Cardoso , Marcio Merino Fernandes , and 1 more author

   In Proceedings of the 2010 IEEE International Symposium on Industrial Electronics , Oct 2010
3. Uma Linguagem para Geração Automática de Arquiteturas Baseadas em Computação Reconfigurável

   Ricardo Menotti, João Manuel Paiva Cardoso , Marcio Merino Fernandes , and 1 more author

   In REC2010: VI Jornadas sobre Sistemas Reconfiguráveis , Oct 2010

2009

1. LALP: A Novel Language to Program Custom FPGA-based Architectures

   Ricardo Menotti, João Manuel Paiva Cardoso , Marcio Merino Fernandes , and 1 more author

   In Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) , Oct 2009
2. Automatic Generation of FPGA Hardware Accelerators Using a Domain Specific Language

   Ricardo Menotti, João Manuel Paiva Cardoso , Marcio Merino Fernandes , and 1 more author

   In International Conference on Field Programmable Logic and Applications (FPL) , Oct 2009

2007

1. Aggressive Loop Pipelining for Reconfigurable Architectures

   Ricardo Menotti, Eduardo Marques , and João Manuel Paiva Cardoso

   In International Conference on Field Programmable Logic and Applications (FPL) , Oct 2007

   Abs

   In this work aims new techniques for mapping software loops to FPGAs. Extensive and aggressive use of pipelining techniques for achieving high performance solutions is the main goal. Those techniques are foreseen to effectively take advantage of the hardware synergies available in the current FPGA devices, especially the DSP blocks and the on-chip configurable memories.

2006

1. A Methodology to Design FPGA-based PID controllers

   J. Lima , R. Menotti , J. M. P. Cardoso , and 1 more author

   In Systems, Man and Cybernetics, IEEE International Conference on , Oct 2006

2004

1. Teaching Embedded Systems with FPGAs Throughout a Computer Science Course

   Vanderlei Bonato , Ricardo Menotti, E. D. V. Simões , and 2 more authors

   In Workshop on Computer Architecture Education (WCAE2004) at 31st International Symposium on Computer Architecture (ISCA) , Oct 2004